DIGITAL-LOGIC SmartModule Express SMX945 Especificaciones Pagina 43
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Checkpoint Description
C2 Set up boot strap processor for POST.
C5 Enumerate and set up application processors.
C6 Re-enable cache for boot strap processor.
C7 Early CPU Init Exit.
0A Initializes the 8042 compatible Keyboard Controller.
0B Detects the presence of PS/2 mouse.
0C Detects the presence of Keyboard in KBC port.
0E
Testing and initialization of different Input Devices. Also, update the Kernel Variables.
Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
Uncompress all available language, BIOS logo, and Silent logo modules.
13 Early POST initialization of chipset registers.
20 Relocate System Management Interrupt vector for all CPUs in the system.
24
Uncompress and initialize any platform specific BIOS modules.
GPNV is initialized at this checkpoint.
2A Initializes different devices through DIM. See section 8.1.5 for more information.
2C
Initializes different devices.
Detects and initializes the video installed in the system that have optional ROMs.
2E Initializes all the output devices.
31
Allocate memory for ADM module and uncompress it. Give control module for initialization.
Initialize language and font modules. Activate ADM module.
33 Initializes the silent boot module. Set the window for displaying information.
37 Displaying sign-on message, CPU information, setup key message, OEM specific information.
38 Initializes different devices through DIM. See section 8.1.5 for more information. USB controllers at this point.
39 Initializes DMAC-1 & DMAC-2.
3A Initialize RTC date/time.
3B
Test for total memory installed in the system. Also, check for keys to limit memory test.
Display total memory in the system.
3C Mid POST initialization of chipset registers.
40
Detect different devices (parallel ports, serial ports, coprocessor CPU, etc.) successfully installed in the system
and update EBDA, etc.
52
Updates CMOS memory size from memory found in memory for Extended BIOS Data Area from base memory.
Programming the memory hole or any kind of implementation that needs in system RAM size if needed.
60 Initializes NUM-LOCK status and programs the KBD typematic.
75 Initialize Int-13 and prepare for IPL detection.
78 Initializes IPL devices controlled by BIOS and option ROMs.
7C Generate and write contents of ESCD in NVRam.
84 Log errors encountered during POST.
85 Display errors to the user and gets the user response for error.
87 Execute BIOS setup if needed / requested. Check boot password if installed.
8C Late POST initialization of chipset registers.
8D Build ACPI tables (if ACPI is supported).
8E Program the peripheral parameters. Enable/Disable NMI as selected.
90
Initialization of system management interrupt by invoking all handlers.
Please note this checkpoint comes right after checkpoint 20h
A1 Clean-up work needed before booting to OS.
A2
Takes care of runtime image preparation for different BIOS modules.
Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table.
Prepares the runtime language module. Disables the system configuration display if needed.
A4 Initialize runtime language module. Display boot option popup menu.
A7
Displays the system configuration screen if enabled.
Initialize the CPUs before boot, which includes the programming of the MTRRs.
A9 Wait for user input at config display if needed.
AA Uninstall POST INT1Ch vector and INT09h vector.
AB Prepare BBS for Int 19 boot. Init MP tables.
AC End of POST initialization of chipset registers. De-initializes the ADM module.
B1 Save system context for ACPI. Prepare CPU for OS boot including final MTRR values.
00 Passes control to OS Loader (typically INT19h).
8.1.4 OEM POST Error Checkpoints
Checkpoints from the range 61h to 70h are reserved for chipset vendors and system manufacturers. The error
associated with this value may be different from one platform to the next.
- Document Revision 100 1
- » Table of Contents « 3
- 1 User Information 6
- 1.6 Technical Support 7
- 1.8 RoHS Commitment 7
- 1.9 Swiss Quality 8
- 2 Introduction 10
- 2.2 Unique Features 11
- 3.1 Microsoft Windows 12
- 3.2 Microsoft Windows XPe 12
- 3.3 Linux 12
- 3.4 Real-time OS 13
- 4 Driver Installation 14
- 4.1.2 VGA 15
- 4.1.1 Chipset 15
- 4.1.3 LAN 16
- 4.1.4 AC97 Sound 17
- 4.1.5 RAID 17
- Enabling RAID in the BIOS 17
- Sound Settings: 27
- 4.4 SpeedStep 28
- 5.1 INT15h SFR Functions 30
- 5.2.1 Int15 Hardware 32
- Resources: 32
- Registers Structure 34
- 6 Memory Specification 36
- 7 Software 37
- 7.2.1 Requirements 38
- 7.2.2 Limitations 38
- 7.2.5 Emulated Features 40
- 8 Diagnostics 41
- 8.1.3 POST Code Checkpoints 42
- 8.1.5 DIM Code Checkpoints 44
- HIGH BYTE XY 44
- 8.2.1 Boot Block Beep Codes 45
- 8.2.2 POST BIOS Beep Codes 45
- 9 BIOS 46
- 9.3 Core BIOS Functions 48
- 9.4 Core BIOS Download 50
- 9.5 BIOS Setup 50
- 9.5.1 Main Menu 51
- 9.5.2 Advanced 51
- CPU Configuration 52
- IDE Configuration 52
- Floppy Configuration 53
- Super I/O Configuration 53
- Health Configuration 54
- ACPI Configuration 54
- APM Configuration 55
- Event Log Configuration 55
- INTEL AMT Configuration 56
- MPS Configuration 56
- PCI Express Configuration 57
- SMBIOS Configuration 57
- Remote Access Configuration 58
- USE Configuration 58
- 9.5.3 PCI PnP 59
- 9.5.4 Boot 60
- Boot Settings Configuration 60
- 9.5.5 Security 61
- 9.5.6 Chipset 61
- Northbridge Configuration 62
- Southbridge Configuration 63
- 9.5.7 Exit 64
- 9.5.8 Remote Access 64
- 9.6 CMOS RAM Map 65
- 11 Index 71
- Corporate Offices 73
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